1. Field of the Invention
The present invention relates to a liquid crystal display and a method of driving the same and, more particularly, to an active matrix liquid crystal display utilizing thin film transistors (TFTs) as switching elements (hereinafter referred to as xe2x80x9cTFT-LCDxe2x80x9d) and a method of driving the same.
2. Description of the Related Art
The recent trend toward TFT-LCDs with higher definition has resulted in an increase in a driving frequency of a gate pulse applied to a gate of each TFT. Further, the trend toward TFT-LCDs with greater screen sizes has resulted in a tendency toward greater wiring lengths and higher wiring resistances of gate bus lines for supplying a gate pulse and data bus lines for outputting grayscale data to a plurality of pixels arranged in the form of a matrix. This results in a problem in that the wiring resistance of a gate bus line can round the gate waveform to cause delays in the timing at which gates are turned off in regions apart from the gate driver. A driving method as shown in FIG. 20 has been adopted in order to avoid this. According to this conventional driving method, the data switching timing of a data voltage Vd output from a data driver to a data bus line is shifted behind the gate-off timing of a gate pulse Vd output from a gate driver to a gate bus line. That is, a predetermined grayscale voltage is applied to a drain electrode of a TFT during a data setup time DS after the gate is turned on, and the same state is maintained for a data holding time DH after the gate is turned off. This makes it possible to write the data voltage Vd in a pixel reliably even if there is a delay in the gate-off timing attributable to rounding of the gate waveform provided that the delay is within the data holding time DH.
However, the greater the panel size of the TFT-LCD, the data holding time DH must be longer. Further, since an output delay time of a data driver increases with the increase of the wiring resistance of the data bus line, the data setup time DS must also increase with the increase of the panel size. On the other hand, an increase in the number of gate bus lines as a result of the trend toward panels with higher definition must be accompanied by a decrease in a horizontal period which is the sum of the data setup time DS and the data holding time DH. That is, in order to satisfy needs for higher definition and greater screen sizes of TFT-LCDs simultaneously, the conventional data driving method must satisfy contradicting requirements for a short horizontal period and a long data holding time DH and data setup time DS.
A normal SVGA (which has 800xc3x97600 pixels) and XGA (which has 1024xc3x97768 pixels) have horizontal periods of 26.4 xcexcs (microseconds) and 20.7 xcexcs, respectively. Therefore, no shortage of data writing time will occur during normal driving as shown in FIG. 20 in which a gate is turned on once in one frame in the case of panels with definition on the level of XGAs having a screen size of 15 inches in the diagonal direction. However, in the case of screens having definition equivalent to or higher than that of an SXGA (which has 1280xc3x971024 pixels) and screen sizes in the excess of 15 inches in the diagonal direction, normal driving may not allow grayscale data to be satisfactorily written. For example, while a normal SXGA must have a horizontal period of 15.6 xcexcm, an SXGA panel having a screen size in the range from about 17 to 18 inches and utilizing the dot inversion driving method to be described later requires a data holding time DH of 3 xcexcs or more and a data setup time DS of 10 xcexcs or more. Therefore, a sufficient margin for data writing may not be provided.
Under such circumstances, a technique has been used in which writing of display data of interest is preceded by pre-writing of display data having the same polarity as means for solving display problems such as irregularity of display and flickers attributable to a shortage of writing of a data voltage.
A description will be made on the pre-writing technique with reference to an example of dot inversion driving in which polarities of grayscale data of adjoining pixels (sub-pixels) are inverted in both of the directions of gate bus lines and data bus lines. In the case of dot inversion driving, the polarity of grayscale data written in a certain pixel is the same as that of grayscale data written in a pixel that is connected to the gate bus line preceding that of the pixel of interest by two lines on the same data bus line. Therefore, pre-writing to the pixel of interest is performed on the line preceding the line of the pixel of interest, in which the primary data are to be written, by two lines. For example, when grayscale data are written in a pixel on the display starting line (first line), the grayscale data are simultaneously pre-written in a pixel on the third gate bus line counted from the display starting line. After that, the primary grayscale data are written in the pixel on the third gate bus line. Therefore, according to this driving method, the gates on the (nxe2x88x922)-th line and n-th line counted from the display starting line are simultaneously turned on. For example, driving methods utilizing pre-writing in such a manner are disclosed in Japanese Patent Laid-Open No. 142807/1999 and No. 265411/1993. A possible method for reserving a sufficient margin for data writing without using pre-writing is to perform frame inversion driving to determine data voltages for bus lines earlier. Frame inversion driving is not preferable in that it results in the problem of crosstalk between data bus lines and pixel electrodes.
As described above, pre-writing of data makes it possible to obtain a sufficient margin for writing even in the case of short gate scanning periods as a result of the trend toward TFT-LCDs with higher definition and short data writing times as a result of the trend toward larger screens.
However, in the case of a conventional driving method utilizing pre-writing, e.g., the above-described dot inversion driving, there is no provision for pre-writing for the first line which is the display starting line among gate bus lines and the second line that follows the first line. The pre-writing for the first and second gate bus lines may be performed during or immediately after the display period of the preceding frame or may alternatively be performing in a vertical blanking period.
When the pre-writing of the first and second lines is performed during or immediately after the display period of the preceding frame, false data are continuously displayed during the period between pre-writing in the preceding frame and primary writing in the current frame. When the vertical blanking period is relatively longer than the display period of a frame, the pre-writing for the first and second lines makes boundaries between those lines and other lines clearly recognizable, which results in a problem in that display quality is reduced.
When the pre-writing for the first and second lines is performed during a vertical blanking period, a problem arises in that it involves a complicated process associated with a virtual gate bus line required for starting the pre-writing. When a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync) are input from the system, since the signals Vsync and Hsync indicate the display starting time, the pre-writing can be started at a line which precedes the line, where display is started, by two lines.
However, according to standard specification for recent LCDs, there is a tendency to determine a display position on a screen based on only a data enable signal Enab supplied from a system without using the signals Hsync and Vsync. This results in a problem in that pre-writing for the first and second lines must be performed during a vertical blanking period based on the data enable signal Enab.
It is an object of the invention to provide a liquid crystal display and a method of driving the same in which pre-writing for at least a first line can be performed in an optimum manner during a vertical blanking period based on a data enable signal Enab from a system.
The above-described object is accomplished by a method of driving a liquid crystal display for controlling timing for outputting display data to a predetermined pixel based on a data enable signal input in association with the input of the display data, characterized in that it has the steps of measuring a period of the data enable signal as a horizontal period, generating a virtual enable signal during a vertical blanking period based on the horizontal period, holding the sum of the data enable signal and virtual enable signal as a vertical period and performing pre-writing of a predetermined display data at least in a pixel at a display starting line at a point in time that precedes the vertical period by an amount which is an integral multiple of the horizontal period.